The present invention relates to a technique to reproduce a PCM signal, and more particularly to method and apparatus for processing an error flag suitable for reproducing a digital audio PCM signal such as rotary head type PCM signal reproduction.
In a PCM signal reproduction apparatus such as a digital audio system, an error of a PCM signal generated in a transmission system including a signal source is detected and corrected. If an incorrectable error is detected in the PCM signal, an audio signal is reproduced by error concealment such as means value interpolation.
As disclosed in U.S. Pat. No. 4,577,319 issued on Mar. 18, 1986 by Takeuchi et al, entitled "Error Flag Processor", which is a continuation of U.S. patent application Ser. No. 422,299 filed on Sept. 23, 1982 and now abandoned, and which was filed based on Japanese Patent Application Nos. 56-153702, 56-153704 and 56-153706 and assigned to the present assignee, an error flag to be added to an incorrectable data is generated by an error correction circuit and written into an error detection/correction code area of a data memory. In this method, the data memory can be effectively utilized but the circuit for generating the error flag is of large scale and the number of times of access to the data memory for writing the error flag increases.